These are my notes on sniffing Ethernet packets with the Radiona ULX3S FPGA.
The verilog source code is surprisingly short. Packet capture and display driver in less that 350 lines of code, including comments.
Keep in mind this is an very primitive and limited example. For one, the arp reply contents are hard coded. Still, it is an impressive proof-of-concept.
Wiring is quite simple: the connectors on etiher side of the ULX3S have pins specifically arranged to allow PMOD modules to be directly connected.
The header on the left side is
J1 with this pinout:
To install, copy the resulting
src/vhd2vlfile to someplace in your
I didn’t have this installed, so:
cd /mnt/c/workspace/ git clone https://github.com/ldoolitt/vhd2vl.git cd vhd2vl make sudo cp ./src/vhd2vl /usr/local/bin/vhd2vl
I already had the yosys/nextpnr/trellis installed:
cd /mnt/c/workspace/ git clone https://github.com/emard/ulx3s-misc.git cd ulx3s-misc/examples/eth/rmii/proj/ make -f makefile.trellis
Note that I was doing this on WSL1, which does not support native USB devices. Thus in the ulx3s-misc/scripts/trellis_main.mk
I needed to make a change to instead call the Windows/DOS exetable version of
# programming tools UJPROG ?= /mnt/c/workspace/fujprog/build/fujprog.exe
In all, it was really quite easy to get it working!
gojimmypi@DESKTOP(WSL): /mnt/c/workspace/ulx3s-misc/examples/eth/rmii/proj (master * u=) emard/ulx3s-misc 0 $ make -f makefile.trellis program /mnt/c/workspace/fujprog/build/fujprog.exe ulx3s_12f_eth_hex.bit ULX2S / ULX3S JTAG programmer v4.6 (git e0cedeb built Aug 1 2020 14:00:08) Copyright (C) Marko Zec, EMARD, gojimmypi, kost and contributors Using USB cable: ULX3S FPGA 12K v3.0.3 Programming: 100% Completed in 5.48 seconds. gojimmypi@DESKTOP(WSL): /mnt/c/workspace/ulx3s-misc/examples/eth/rmii/proj (master * u=) emard/ulx3s-misc 0 $