Some notes on RISC-V debugging.
There are JTAG interfaces avilable on many hardware devices for single-step debugging code. But what about a softcore CPU built on an FPGA?
I asked on Twitter, and received some excellent responses:
First, Tom Verbeure has an excellent blog on VexRiscv, OpenOCD, and Traps. He also mentioned Implementing VexRiscv Based Murax SoC on Arty A7 Artix-7 PCB from Digilent and Enabling JTAG Connection through Xilinx BSCANE2 Debug IP
There’s also two interesting resources from @Ruinland_Mask for this JTAG Debug Transport Module TAP Spec in the riscv/riscv-debug-spec repo, as well as reference implmeneation RISC-V Debug Support for PULP Cores and this DTM in VHDL called the NEORV32 - RISC-V Debug Transport Module.